Ball Grid Array (BGA) packaging technology, which is a well-known advanced technology in the relevant art, is performed in a manner as to mount a semiconductor chip on a front side of a substrate and implant a grid array of solder balls on a back side of the substrate. The solder balls are used to electrically connect the entire package unit to an external printed circuit board. The BGA packaging technology advantageously incorporates more I/O (input/output) connections within the same unit area of a chip carrier (e.g. the substrate) such that the high integration requirement of the semiconductor chip is satisfied.
The highly integrated semiconductor chip during operation usually produces a large amount of heat. As the semiconductor chip is encapsulated by an encapsulant that is made of a resin material having poor thermal conductivity (a coefficient of thermal conductivity thereof is only 0.8 w/m-k), the heat produced from the semiconductor chip cannot be effectively dissipated through the encapsulant. This results in unsatisfactory heat dissipating efficiency and adversely affects the performance and lifetime of the semiconductor chip.
Accordingly, a thermally enhanced BGA semiconductor package incorporated with a heat dissipating structure has been proposed in order to improve the heat dissipating efficiency of the semiconductor package.
As shown in FIG. 1 for a semiconductor package 1 disclosed by U.S. Pat. No. 5,726,079, there is a heat sink 11 directly attached to a chip 10, wherein a top surface 11a of the heat sink 11 is exposed to the atmosphere from an encapsulant 12 that encapsulates the chip 10, such that heat generated by the chip 10 can be transferred to the heat sink 11 and dissipated to the atmosphere without having to pass through the encapsulant 12 that has poor thermal conductivity.
However, the semiconductor package 1 causes significant drawbacks during fabrication thereof. After the heat sink 11 is attached to the chip 10, the structure of combined heat sink 11 and chip 10 is placed into a mold cavity of an encapsulation mold (not shown) to perform a molding process for forming the encapsulant 12. As the top surface 11a of the heat sink 11 is intended being exposed, the top surface 11a must abut against a top wall of the mold cavity during molding. However, if the top surface 11a of the heat sink 11 fails to effectively abut against the top wall of the mold cavity, resin flashes of the encapsulant 12 are formed on the top surface 11a of the heat sink 11, which not only deteriorate the heat dissipating efficiency but also impair appearance of the fabricated product. In such case, an additional deflashing process is usually required to remove the flashes, which undesirably prolongs the fabrication time, increases fabrication costs, and possibly damages the fabricated product. On the other hand, too close contact between the heat sink 11 and the top wall of the mold cavity may lead to cracking of the fragile chip 10 by excessive pressure from the encapsulation mold.
In particular, if a distance between the top surface 11a of the heat sink 11 and an upper surface of a substrate 13 where the chip 10 is mounted is larger than a depth of the mold cavity, during the molding process, the heat sink 11 is pressed by the upper mold and thus the chip 10 directly in contact with the heat sink 11 is cracked. On the contrary, if the distance between the top surface 11a of the heat sink 11 and the upper surface of the substrate 13 is smaller than the depth of the mold cavity, resin flashes of the encapsulant 12 are formed on the top surface 11a of the heat sink 11 during molding, which undesirably decrease an exposed area of the top surface 11a of the heat sink 11 and reduce the heat dissipating efficiency.
To make the distance between the top surface 11a of the heat sink 11 and the upper surface of the substrate 13 equal to the depth of the mold cavity, attachment between the chip 10 and the heat sink 11, attachment between the chip 10 and the substrate 13, and the thickness of the heat sink 11 must be precisely performed and controlled, such that the packaging costs and process complexity in fabrication are increased. Further by such requirement on precision, the heat sink 11 can only be attached to the chip 10 one by one rather than a batch-type method, thereby increasing the fabrication time and reducing the packaging efficiency.
Since the heat dissipating efficiency of the semiconductor package 1 is proportional to the exposed area of the top surface 11a of the heat sink 11, the heat sink 11 when having the same surface area as the semiconductor package 1 would have the maximum exposed area to provide the maximum heat dissipating efficiency under a condition with a constant size of the semiconductor package 1. To achieve this arrangement, sides of the heat sink should be flush or engaged with side walls of the mold cavity during the molding process. However, if the heat sink is inaccurately fabricated and oversized, it cannot be successfully placed into the mold cavity; or, if the heat sink is undersized, resin flashes of the encapsulant may easily occur on the top surface or sides of the heat sink. Therefore, such structural arrangement causes a yield concern and difficulty in fabrication.
In view of the foregoing drawbacks, U.S. Pat. Nos. 6,458,626 and 6,444,498 disclose a semiconductor package with a heat sink being directly attached to a chip without causing chip cracking or resin flashes on an exposed surface of the heat sink, as shown in FIGS. 2A to 2C and FIG. 3. In this semiconductor package, an interface layer 25 is formed on a surface of a heat sink 21 to be exposed to the atmosphere, and has poor adhesion with an encapsulant 24 or the heat sink 21. Then, the heat sink 21 is directly attached to a chip 20 mounted on a substrate 23. A molding process is performed to form the encapsulant 24 for encapsulating the heat sink 21, the chip 20 and the interface layer 25 on the heat sink 21 (as shown in FIG. 2A). The depth of a mold cavity of an encapsulation mold used in the molding process is made larger than the sum of the chip 20 and the heat sink 2 in thickness, such that the encapsulation mold does not come into contact with and press the heat sink 21 and the chip 20 is not cracked during molding. Subsequently, a singulation process is performed (as shown in FIG. 2B), and the encapsulant 24 above the heat sink 21 is removed. If the adhesion between the heat sink 21 and the interface layer 25 (such as a plated gold layer) is larger than that between the interface layer 25 and the encapsulant 24, the interface layer 25 remains on the heat sink 21 after the encapsulant 24 above the heat sink 21 is removed, and no residue of the encapsulant 24 is left on the heat sink 21 (as shown in FIG. 2C), thereby no flash problem. On the contrary, if the adhesion between the interface layer 25 (such as an adhesive tape made of polyimide resin) and the heat sink 21 is smaller than that between the interface layer 25 and the encapsulant 24, the interface layer 25 is removed together with removal of the encapsulant 24 above the heat sink 21 (as shown in FIG. 3), such that no flash of the encapsulant 24 occurs on the heat sink 21.
However, during the singulation process for the above semiconductor package, a cutting tool is required to directly cut through the heat sink that is typically made of a relatively thick and rigid metal, such that uneven cutting sides having acute-angled saws or burrs are produced at peripheral sides of the singulated heat sink no matter whether a punching method or a diamond cutting tool is used for singulation. This drawback not only adversely influences the appearance of the semiconductor package but also makes the punching tool or the cutting tool wear faster, thereby leading to a great increase in cost and decrease in production efficiency.
Therefore, the problem to be solved here is to provide a heat dissipating semiconductor package and a fabrication method thereof, which can overcome the foregoing drawbacks